1. Field of the Invention
The present invention relates to a data-hold timing adjustment circuit which adjusts the deviations in hold timings of bits of parallel data in flip-flops or latch circuits or the like caused by propagation delays of a clock through a clock line.
2. Description of the Related Art
In a semiconductor integrated circuit such as a DRAM, for example, 256-bit parallel data are written in synchronization with a clock in one line of 256.times.256 memory cells which is specified with a column address, and each line is considered to be a 256-bit register. In a register with a great number of bits such as this, the timing with which parallel data are held in the register in synchronization with the clock becomes problematic, as described below, at higher operating speeds.
In FIG. 7A, the register 10 consists of n number of D flip-flops 11 to 1n, and each D flip-flop is provided with a data input end and a pair of clock input ends. Each D flip-flop holds data supplied to the data input end in synchronization with one pair of complementary clocks .phi. 1 and * .phi. 1 which are supplied to the clock input ends. The clocks .phi. 1 and * .phi. 1 are generated from the clock .phi. via a clock buffer circuit 20. The output ends of the inverters 21 to 2n are connected to the data input ends of the D flip-flops 11 to 1n respectively and the n-bit parallel data D1 to Dn are supplied to the D flip-flops 11 to 1n via the inverters 21 to 2n.
The relationship between the clock .phi. and the data D1 and Dn is illustrated in FIG. 7B. The set-up time ts and the hold time th are both set at, for example, 1ns. The relationship between the clock .phi. 1 supplied to the clock input end of the D flip-flop 11 and the data d1 supplied to the data input end of that is illustrated in FIG. 7C and it is identical to the relationship shown in FIG. 7B.
However, since the pairs of clock input ends in each of the D flip-flops 11 to in are commonly connected via the clock input line, the clock is propagated with different delays through this clock input line to the clock input ends of the D flip-flops 11 to 1n. Because of this, the relationship between the clock .phi. n that is supplied to the clock input end of the D flip-flop 1n, which is the farthest from the clock buffer circuit 20, and the data dn that is supplied to the data input end of the D flip-flop 1n, is as shown in FIG. 7C; that is, the margin of the hold time th is reduced as the data-hold timing deviates and if the clock frequency is increased to facilitate high speed operation, this will cause errors or restriction of high speed operation.
In the prior art, in order to adjust this deviation in the data-hold timing, multi-stage inverters are connected to its data input ends such that the number of stages is larger as the clock delay is longer.
However, since it is necessary to change the stages of inverters to be connected depending upon the number of bits n of the register 10, the structure must be altered according to the number of bits. Also, the layout area required for the inverters is considerable and, since the area for for all the inverters is secured in a rectangle, the fewer the stages of inverters, the higher the ratio of dead space.